Computing devices are common in modern society. The ease with which such computing devices perform myriad functions is enabled through complex integrated circuits instantiated on separate chips. In many instances different circuits on separate chips may need to communicate with one another inside the computing device. Such interchip communication may be effectuated by a serial data bus.
As the level of complexity increases, the amount of data that needs to be transferred between chips increases. There are generally two ways to increase the rate of data transfer. The first way is to increase the number of data channels between the chips by increasing the pin count on the chips and routing appropriate conductors between the pins. Each data channel may be a separate serial data channel, but collectively they may be considered a parallel bus. Increases in the number of data channels through additional pins and conductors is relatively expensive and may lead to design complications as the extra conductors must be routed in such a manner that limits electromagnetic interference and area consumption. The second way is to increase the clock frequency associated with the data channel. Increases in clock frequency may generate additional electromagnetic interference concerns.
Accordingly, there is a desire to increase options available to circuit designers for improved serial data transmission across a single data channel.